Fuzzy Logic and VLSI Testing

Abstract

A new application of Fuzzy logic (FL), in the context of test vector generation in VLSI testing is presented. Fuzzification of the threshold value simulation (TVS) approach and setting up of mathematical concepts are carried out in terms of a hierarchy of membership functions. The test-vectors are found by optimising a suitable membership function. The Fuzzy model besides giving a different mathematical basis, also helps in defining new and better optimising functions, thus provind its utility. The concepts outlined in this paper, though demonstrated on toy model of a circuit consisting of only AND gates, can easily be extended to circuits with other logic gates.