New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Keywords: 681.3 Computer Science
AbstractA new algorithm for test-vector-generation (TVG) for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.
How to Cite
Atre, M., & Latha, V. (2013). New Metric Based Algorithm for Test Vector Generation in VLSI Testing. Defence Science Journal, 45(3), 255-265. https://doi.org/10.14429/dsj.45.4132
Computers & Systems Studies
Copyright (c) 2016 Defence Science Journal
where otherwise noted, the Articles on this site are licensed under Creative Commons License: CC Attribution-Noncommercial-No Derivative Works 2.5 India