Design of Triple Gate for Sub threshold Low Power applications
Abstract
A novel design of triple gate MOSFET structure with metal gate and an underlap channel is proposed to minimise the short channel and corner effects. The gate metal used is titanium nitride as well as source and drain is diffused with titanium nitride so as to increase the drive capability of the device. To obtain subthreshold threshold voltage operation of the device, the gates are kept symmetric and the gate electrodes corner segments are rounded off to minimise leakage. The device shows significant improvement over conventional double gate FinFET and triple gate device without gate corner round off device in terms of Ion, Ioff ratio, DIBL, subthreshold slope, rise time, fall time.
References
D.Mitra and C.K.Maiti, “25-nm Triple gate FinFETs with Raised Source Drain: A 3D simulation study”, IETE Mumbai centre, NateHCA, 2007, pp.57-61
S. Cristoloveanu, 2008, “How Many Gates Do We Need in A Transistor: One, Two, Three or Four?”, Romanian Journal Of Information Science and technology, Volume 11, Number 1, pp.17- 28
Scott Thompson, Paul Packan, and Mark Bohr, “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal Q3’98, pp.1-19.
J.P.Colinge, 2008, “The New Generation of SOI MOSFETs”, Romanian Journal of Information Science and Technology, Volume 11, Number 1, 3-15
D. Nirmal, P. Vijayakumar,Divya Mary Thomas, Binola K. Jebalin, N. Mohankumar, “Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics”, Microelectronics Reliability 53, October 2012
Kumar.M.P, Gupta.S.K, Paul.M, “Corner effects in SOI Trigate FinFETstructure by using 3Dprecess and devie simulations”, ICCCSIT, 2010, vol9, pp.704-707
M.Mustafa, Tawseef.A.Bhat, M.R.Beigh, “threshold voltage sensitivity to metal gate work function based performance evaluation of Double gate n-finFET structures for LSTP technology, World Journal of Nanoscience and Engineering, 2013, 3 , 17-22
M.H.Chiang, J.N.Lin, K.Kim, C.T.Chuang,”Asymmetrical Tiple Gate FET, Simulation of Semiconductor processes and devices, 2007, Vol.12, pp.389-396
S.L.Wu, S.P.Chang, S.J.Chang, H.F.Chiu, Y.S.Chang, O.Cheng, “Work Function Tuing in Metal/High K nFinFETs, IEEE Nanotechnology materials and devices conference, 2013, pp.1-7
Where otherwise noted, the Articles on this site are licensed under Creative Commons License: CC Attribution-Noncommercial-No Derivative Works 2.5 India