Design of Triple Gate for Sub threshold Low Power applications

  • Flavia Princess Nesamani ASSISTANT PROFESSOR, DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING, KARUNYA UNIVERSITY, COIMBATORE-641114
  • Geetanjali Raveendran Estee Lauder, Manhattan, NYC
  • V.Lakshmi Prabha Government College of Technology, Coimbatore-13,
Keywords: Triple Gate MOSFET, Metal Gate, Underlap channel, AC analysis

Abstract

A novel design of triple gate MOSFET structure with metal gate and an underlap channel is proposed to minimise the short channel and corner effects. The gate metal used is titanium nitride as well as source and drain is diffused with titanium nitride so as to increase the drive capability of the device. To obtain subthreshold threshold voltage operation of the device, the gates are kept symmetric and the gate electrodes corner segments are rounded off to minimise leakage. The device shows significant improvement over conventional double gate FinFET and triple gate device without gate corner round off device in terms of Ion, Ioff ratio, DIBL, subthreshold slope, rise time, fall time.

Author Biographies

Flavia Princess Nesamani, ASSISTANT PROFESSOR, DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING, KARUNYA UNIVERSITY, COIMBATORE-641114

Ms I. Flavia Princess Nesamani obtained BE in Electrical Engineering from Madras University in 1998, ME from Anna University, Chennai and currently pursuing PhD in Anna University, Coimbatore. She is working as programme coordinator and assistant professor in the Department of Electrical Technology in Karunya University and her area of interests are low power VLSI, Nano Device Modelling, Nano particle synthesis, etc.

Geetanjali Raveendran, Estee Lauder, Manhattan, NYC

Ms Geetanjali Raveendran obtained MTech (VLSI Design) from Karunya University in 2013. Her area of research includes Nano Device Modelling and Low Power VLSI Design.

V.Lakshmi Prabha, Government College of Technology, Coimbatore-13,

Dr V. Lakshmi Prabha received BE in Electronics and Communication Engineering from Madras University in 1980, ME in Applied Electronics from Bharathiar University in 1986, received PhD in the area of Low power VLSI design in the year 2008 from Anna University, Chennai. She underwent training, in 2007, at the Embedded Systems Lab, Virginia Tech University, USA.

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Published
2017-03-14
How to Cite
Nesamani, F., Raveendran, G., & Prabha, V. (2017). Design of Triple Gate for Sub threshold Low Power applications. Defence Science Journal, 67(2), 169-172. https://doi.org/10.14429/dsj.67.10067
Section
Special Issue Papers