Implementation of a Prototype Cellular Logic Array Processor

  • A. Mukherjee Indian Institute of Science, Bangalore
  • Y. V. Venkatesh Indian Institute of Science, Bangalore
Keywords: CLAP 4, Parallel architecture, TTL integrated circuits

Abstract

A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using TTL integrated circuits, can process 8 by 4 arrays of 4-bit image data in parallel, i.e. simultaneously, as a consequence of the parallel architecture which enables acceptance of contextual information from the neighbourhood of a pixel. Further CLAP-4 provides 48 arithmetic/logical operations on (up to) three operand images. In this paper, a description of the structure of CLAP-4 is presented.

Author Biographies

A. Mukherjee, Indian Institute of Science, Bangalore
Indian Institute of Science, Bangalore-560012
Y. V. Venkatesh, Indian Institute of Science, Bangalore
Indian Institute of Science, Bangalore-560012
Published
2014-01-24
How to Cite
Mukherjee, A., & Venkatesh, Y. (2014). Implementation of a Prototype Cellular Logic Array Processor. Defence Science Journal, 35(3), 353-359. https://doi.org/10.14429/dsj.35.6028
Section
Special Issue Papers