Implementation of a Prototype Cellular Logic Array Processor

Abstract

A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using TTL integrated circuits, can process 8 by 4 arrays of 4-bit image data in parallel, i.e. simultaneously, as a consequence of the parallel architecture which enables acceptance of contextual information from the neighbourhood of a pixel. Further CLAP-4 provides 48 arithmetic/logical operations on (up to) three operand images. In this paper, a description of the structure of CLAP-4 is presented.