Field-Programmable Gated Array Implementation of Split-Radix Fast Fourier Transform for High Throughput

Abstract

As the signal processing required in electronic warfare (EW) domain is complex and the sample rates to be handled are very high, IP cores which are freely available are not of much use. A study of various fast fourier transform (FFT) algorithms has been carried out and spit-radix FFT has been chosen to be implemented due to fewer multiplications3.This algorithm is attractive to be implemented using field-programmable gated array (FPGA). This paper presents split-radix FFT algorithm for implementation of 512-pt FFT on FPGA platform for EW applications. The algorithm is such designed that it can achieve a throughput of up to 1500 MSPS. 512-pt SRFFT is implemented using parallel pipelined architecture in order to maximize processing speed and thus achieve a throughput of 1500 MSPS with area optimization. The pipeline structure is partitioned to balance the input throughput and to optimize the available FPGA resources. The standard Cooley-Tukey radix-2 FFT algorithm requires N/2 log2 N (for N=512, 2304 multiplications)multiplications and N log2 N additions where as radix-4 FFT requires N/2 log4 N multiplications and N log2 N additions. The SRFFT presented in this paper has a multiplicative complexity of only about two-thirds that of the radix-2 FFT, and is better than the radix-4 FFT or any higher power-of-two radix as well. The initial latency is less than N clock cycles.

Defence Science Journal, 2013, 63(2), pp.210-213, DOI:http://dx.doi.org/10.14429/dsj.63.4266