Generation of High Power Test Vector Set for Combinational VLSI Circuits

K.T. Oornmen Tharakan; S.S.S.P. Rao

doi:10.14429/dsj.52.2190

K.T. Oornmen Tharakan Vikram Sarabhai Space Centre, Thiruvananthapuram
S.S.S.P. Rao Indian Institute of Technology Bombay, Mumbai

DOI: https://doi.org/10.14429/dsj.52.2190

Keywords: Bum-in simulation, latent defects, failure mechanisms, burn-in test vectors, stress testing, VLSI devices, VLSI circuits, CMOS signal switching, power vectors, algorithm, CMOS gates, CMOS device, complementary metal oxide semiconductor device

Abstract

"Burn-in is a well-known technique that helps to accelerate failure mechanisms to surface out latent defects, which are not activated during normal testing of the VLSI devices. The devices are kept at a specified high temperature, for a specified period, in static or dynamic conditions. Since this method is cumbersome, an alternate method based on complementary metal oxide semiconductor (CMOS) signal switching for VLSI devices is considered. The majority of power dissipation in CMOS circuitry is due to the switching current associated with charging and discharging of load capacitances. Hence, if the test vectors can be so designed that maximum activity is conjured, the stress on the device can be maximised. In this paper, a new algorithm for generation of these power vectors from a gate-level description of the circuit is presented. The method has been applied to different circuits and the results compared.