Optimising Model for Memory Fault Tolerance in Onboard Computer
Keywords: Reliability, fault tolerance, optlmising model, memory erron, error correction logic, onboard computer, mission critical systems, real-time systems
AbstractThis paper presents an optimising model for integrating the traditional reliability prediction methodology with simple analytical techniques to facilitate the designer to decide upon the memory fault-tolerant choices of an onboard computer. In this exercise, the hardware reliability estimates of a circuit without any error correction as well as that of a circuit with error detection and correction were calculated. The failure rates of each component and soldering have been accounted for in these prediction procedures. A suitable probability distribution is chosen for data errors and is analytically combined with the hardware reliability predictions to study the trade-offs. An optimum strategy for introducing the hardware error correction logic in the circuit is presented.
How to Cite
Mathew, S. V., Punnekkat, S., & Saiam, A. (2002). Optimising Model for Memory Fault Tolerance in Onboard Computer. Defence Science Journal, 52(1), 33-39. https://doi.org/10.14429/dsj.52.2146
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