Development of an Abstract Model for a Non-volatile Static Random Access Memory

K.T. Oommen Tharakan; A. N. Chandorkar; S.S. S.P. Rao

doi:10.14429/dsj.54.2031

K.T. Oommen Tharakan Indian Institute of Technology Bombay, Mumbai
A. N. Chandorkar Indian Institute of Technology Bombay, Mumbai
S.S. S.P. Rao Indian Institute of Technology Bombay, Mumbai

DOI: https://doi.org/10.14429/dsj.54.2031

Keywords: Memory devices, non-volatile static random access memory (NVSRAM), memory fault modelling algorithm, random access memory, models, fault models, non-volatile memory, static random access memory (SRAM)

Abstract

The capability to protect against power fluctuations, which eventually prevents the corruption of the memory contents makes non-volatile static random access memory a very good choice for use in highly reliability applications. These random access memories are protected against data writing in addition to preserving the desired contents. Energy source and control circuitries are embedded into it for achieving the same. The control circuitry constantly monitors supply voltage level, inhibits data corruption, and switches on the energy source once it falls beyond a threshold level. In this paper, development of an abstract model for such a non-volatile static random access memory chip has been presented. Test sequences based on this model have been generated for this memory chip. These test sequences have been implemented in VLSI tester and exercised on the chips.