A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture

Ganesh Garga; Saptarsi Das; S. K. Nandy; Ranjani Narayan; Chandan Haldar; Maheshkumar P. Jagtap; Siba Prasad Dash

doi:10.14429/dsj.62.1438

Ganesh Garga Morphing Machines Pvt Ltd., Bengaluru
Saptarsi Das Indian Institute of Science, Bengaluru
S. K. Nandy Indian Institute of Science, Bengaluru
Ranjani Narayan Morphing Machines Pvt Ltd., Bengaluru
Chandan Haldar Morphing Machines Pvt Ltd., Bengaluru
Maheshkumar P. Jagtap Advanced Numerical Research and Analysis Group, Hyderabad
Siba Prasad Dash Advanced Numerical Research and Analysis Group, Hyderabad

DOI: https://doi.org/10.14429/dsj.62.1438

Keywords: REDEFINE, advanced encryption standard, AES, elliptic curve cryptography, ECC, cryptographic protocols

Abstract

The highest levels of security can be achieved through the use of more than one type of cryptographic algorithm for each security function. In this paper, the REDEFINE polymorphic architecture is presented as an architecture framework that can optimally support a varied set of crypto algorithms without losing high performance. The presented solution is capable of accelerating the advanced encryption standard (AES) and elliptic curve cryptography (ECC) cryptographic protocols, while still supporting different flavors of these algorithms as well as different underlying finite field sizes. The compelling feature of this cryptosystem is the ability to provide acceleration support for new field sizes as well as new (possibly proprietary) cryptographic algorithms decided upon after the cryptosystem is deployed.

Defence Science Journal, 2012, 62(1), pp.25-31, DOI:http://dx.doi.org/10.14429/dsj.62.1438

Author Biographies

Ganesh Garga, Morphing Machines Pvt Ltd., Bengaluru

Mr Ganesh Garga has obtained his MSc(Engg.) from the Indian Institute of Science (IISc), Bengaluru, in 2009. He is currently working as a Senior Member of Technical Staff at Morphing Machines Pvt. ltd, Bengaluru, India. His research interests area: Cryptographic processors and wireless baseband systems.

Saptarsi Das, Indian Institute of Science, Bengaluru

Mr Saptarsi Das received his BE from Jadavpur University, Kolkata in 2007 and MSc from IISC, Bengaluru, in 2011. He is currently pursuing his PhD from IISc, Bengaluru. His research interests include: Applied cryptography and reconfigurable computing.

S. K. Nandy, Indian Institute of Science, Bengaluru

Dr SK Nandy has received MSc (Engg.) in Computer Science and Engineering in 1986 and the PhD (Computer Science and Engineering) from IISC, Bengaluru, in 1989. He is currently working as a Professor in the Supercomputer Education and Research Centre, IISc, Bengaluru. He has over 150 publications in International Journals, and Proceedings of International Conferences. His research interests includes: low power and high performance embedded systems on a chip, VlSI architectures for reconfigurable systems on chip, and architectures and compiling techniques for heterogeneous many core systems.

Ranjani Narayan, Morphing Machines Pvt Ltd., Bengaluru

Dr Ranjani Narayan obtained her PhD from IISC, Bengaluru, in 1989. Currently she is the CTO of Morphing Machines, Pvt ltd, Bengaluru. She has many publications in Journals and proceedings of International Conferences to her credit. Her research interests include: Processor architectures, heterogeneous multi-cores architectures, embedded SoCs, and reconfigurable silicon cores.

Chandan Haldar, Morphing Machines Pvt Ltd., Bengaluru

Dr Chandan Haldar received hid BTech (Honors) and MTech from Indian Institute of Technology, Kharagpur and PhD from IISc, Bengaluru. He is currently working as a Managing Director of Morphing Machines Pvt ltd, Bengaluru. He is also Chairman and Chief Scientist at Terra Incognitus Systems Research Alliance Pvt ltd (TISRA). He is an alumnus of the Senior Executive Programme at the London Business School as Aditya Birla Scholar, and a Senior Member of the ACM, IEEE, and IEEE Computer Society.

Maheshkumar P. Jagtap, Advanced Numerical Research and Analysis Group, Hyderabad

Mr Maheshkumar P. Jagtap has obtained BE (Electronics) from University of Poona. He is currently working as a Scientist F at Advanced Numerical Research and Analysis Group (ANURAG), Hyderabad. His research interests are: Multi-core processor architectures, multi-core processor based system, flexible cryptographic processor architecture, reconfigurable computing system on chip, and network processor architecture for security and high performance applications.

Siba Prasad Dash, Advanced Numerical Research and Analysis Group, Hyderabad

Mr Siba Prasad Dash has obtained BE(Electronics and Telecommunication) from North Maharashtra University. He is currently working as a Scientist C in the ANURAG, Hyderabad. His research interests are: Multicore processor, flexible cryptography processor architecture, architecture for secure routers and switches.