Design for Stuck-at Fault Testability in MCT based Reversible Circuits

  • Hari Mohan Gaur Department of Electronics & Communication Engineering, National Institute of Technology, Kurukshetra, India
  • Ashutosh Kumar Singh
  • Umesh Ghaneka
Keywords: Reversible Logic Circuits, Design for Testability, Fault Detection.


Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. This paper presents a new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits. The circuit is modified in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. An (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modification methodology is experimented on a set of benchmarks. The present work achieved a reduction up to $50.58\%$ in operating costs as compared to the existing work implemented on the same platform.


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How to Cite
Gaur, H., Singh, A., & Ghaneka, U. (2018). Design for Stuck-at Fault Testability in MCT based Reversible Circuits. Defence Science Journal, 68(4), 381-387.
Electronics & Communication Systems