Design for Stuck-at Fault Testability in MCT based Reversible Circuits

Hari Mohan Gaur; Ashutosh Kumar Singh; Umesh Ghaneka

doi:10.14429/dsj.68.11328

Hari Mohan Gaur Department of Electronics & Communication Engineering, National Institute of Technology, Kurukshetra, India http://orcid.org/0000-0002-7952-4899
Ashutosh Kumar Singh
Umesh Ghaneka

DOI: https://doi.org/10.14429/dsj.68.11328

Keywords: Reversible Logic Circuits, Design for Testability, Fault Detection.

Abstract

Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. This paper presents a new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits. The circuit is modified in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. An (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modification methodology is experimented on a set of benchmarks. The present work achieved a reduction up to $50.58\%$ in operating costs as compared to the existing work implemented on the same platform.

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