A FPGA based Steganographic System Implementing a Modern Steganalysis Resistant LSB Algorithm

Abstract

Steganography differs from other data hiding techniques because it encodes secret message inside cover object in such a way that transmission of secret message also remains a secret. Widespread usage of digital images, lower computational complexity and better performance makes spatial domain steganographic algorithms well suited for hardware implementation, which are not very frequent. This work tries to implement a modern steganalysis resistant LSB algorithm on FPGA based hardware. The presented work also optimises various operations and elements from original one third probability algorithm with respect to hardware implementation. The target FPGA for the implementation is Xilinx SP605 board (Spartan 6 series XC6SLX45T FPGA). Stego images obtained by the implementation have been thoroughly examined for various qualitative and quantitative aspects, which are found to be at par with original algorithm.