THARAKAN, K. O.; RAO, S. Generation of High Power Test Vector Set for Combinational VLSI Circuits. Defence Science Journal, [S. l.], v. 52, n. 4, p. 351–356, 2002. DOI: 10.14429/dsj.52.2190. Disponível em: https://publications.drdo.gov.in/ojs/index.php/dsj/article/view/2190. Acesso em: 19 oct. 2025.