TY - JOUR AU - Suresh V. Mathew AU - Sasikumar Punnekkat AU - Abdul Saiam PY - 2002/01/01 Y2 - 2024/03/29 TI - Optimising Model for Memory Fault Tolerance in Onboard Computer JF - Defence Science Journal JA - DSJ VL - 52 IS - 1 SE - Special Issue Papers DO - 10.14429/dsj.52.2146 UR - https://publications.drdo.gov.in/ojs/index.php/dsj/article/view/2146 AB - This paper presents an optimising model for integrating the traditional reliability prediction methodology with simple analytical techniques to facilitate the designer to decide upon the memory fault-tolerant choices of an onboard computer. In this exercise, the hardware reliability estimates of a circuit without any error correction as well as that of a circuit with error detection and correction were calculated. The failure rates of each component and soldering have been accounted for in these prediction procedures. A suitable probability distribution is chosen for data errors and is analytically combined with the hardware reliability predictions to study the trade-offs. An optimum strategy for introducing the hardware error correction logic in the circuit is presented. ER -