Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

The high-k is needed to replace SiO2 as the gate dielectric to reduce the gate leakage current. The impact of a high-k gate dielectric on the device short channel performance and scalability of nanoscale double gate Fin field effect transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high-k at the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer-aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified as VT=0.653V with ε=23(ZrO2) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47×10-14 A. High-k improves the Ion/Ioff ratio of transistors for future high-speed logic applications and also improves the storage capability.

As conventional scaling of classical CMOS is approaching technological limits, interest in non-classical double-gate and triple-gate is growing. These multi-gate devices, which can be fabricated as fin field effect transistors (FinFETs), are potentially scalable to the end of ITRS because of their ultra-thin bodies which suppress short channel effects owing to the simultaneous control of the channel by more than one gate. Here, self-aligned processes have been introduced where the FinFET concept is one of the most promising1 FinFETs have several advantages, including better current control without requiring increased device size. FinFETs facilitate scaling of CMOS dimensions while maintaining acceptable performance2.

Alternative dielectric materials other than silicon with a higher dielectric constant, k, and thus, larger physical thickness than SiO2 are required to reduce the gate leakage current and provide high on-currents3. The implementation of high-k dielectrics to the SOI (silicon-on-insulator) FinFETs improves the scalability and saves chip area. A high-k dielectric material needs to provide good electrical stability, that is, the amount of charge trapped in the high-k dielectric material needs to remain at a low level even after extended operation of a transistor. It should also be scalable, that is, it should provide an acceptable level of leakage and acceptable levels of electron and hole mobility at reduced thickness. High-k dielectric materials satisfying these conditions may be advantageously employed for high performance semiconductor devices1-4. Also the larger physical thickness thk of the high-k dielectric reduces the parasitic gatesource/drain (G-S/D) outer fringe capacitance5. Using technology computer-aided design (TCAD) tools, FinFET device models and simulations can be performed to evaluate the performance of FinFETs for high performance, low operating power, and low standby power applications according to International Technology Roadmap for Semiconductors (ITRS) specifications6. The performance and characteristics of a FinFET device is created and the simulations are performed on it. High-k improves the Ion/Ioff ratio of transistors for future high speed logic applications and also improves the storage capability7.

The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for manufacturing fin field effect transistors. The push for ever increasing device densities is particularly strong in CMOS technologies, such as in the design and fabrication of field effect transistors (FETs)8. Scaling FETs to attain higher device density in CMOS results in degradation of performance and/or reliability9.

The gate of the FinFET is then formed on one or more sides of the fin. FinFETs have several advantages, including better current control without requiring increased device size. FinFETs thus facilitate scaling of CMOS dimensions while maintaining an acceptable performance9.

FinFET devices need to be isolated from each other, and the source and drain of individual devices need to be isolated to ensure source-to-drain decoupling. For this reason, FinFETs have been typically manufactured from silicon-on-insulator (SOI) wafers to provide isolation between the fins of different devices. The source and drains of individual FinFETs are decoupled from each other by the buried isolation layer.

In recent years, MOSFET devices have been aggressively scaled in combination with a complex design of the channel doping to avoid short channel effects. One approach to avoid gate tunnelling is the use of thicker gate oxides of different materials (high-k materials)10. Multi-gate MOSFETs have been considered one of the most attractive devices to achieve channel lengths < 20 nm. To completely control the silicon area between the gates, the silicon area must be fully depleted. Short channel effects can be avoided using very thin membranes or fins. The alignment of the gates to each other and to the implanted doping profiles is very crucial for the device performance and constitutes one of the key issues for multi-gate device manufacturing. Therefore, self-aligned processes have been introduced and FinFET devices with gate lengths down to 18 nm and a gate oxide thickness of 2.5 nm have been tested experimentally. Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45 nm CMOS technologies.

One of the most promising structures is the FinFET with a double gate that is wrapped around a narrow silicon fin, which provides robustness against short-channel effects. A thinner body allows for more aggressive gate-length scaling. Short channel effects can be avoided using very thin membranes or fins. FinFETs have several advantages, including better current control without requiring increased device size. FinFETs thus facilitate scaling of CMOS dimensions while maintaining an acceptable performance11. Most of the reported results that describe experiments rely on simplified two-dimensional simulations. Only few three-dimensional investigations have been performed for FinFET structures. Three-dimensional simulations are, therefore mandatory to properly predict the behaviour of such devices.

2.1 Short Channel Effects

The short channel effects occur when the magnitude of the width of the depletion region between the source and drain is equal to the channel length of the MOSFET. Short channel effect means decrease in threshold voltage as channel length decreases. As the channel length L is reduced to increase both the operation speed and the number of components per chip, short channel effect arises12. The short-channel effects are attributed to the following two physical phenomena:

• The limitation imposed on electron drift characteristics in the channel.

• The modification of the threshold voltage due to the shortening channel length.

To fulfil the scaling scenario as projected in the International Technology Roadmap for Semiconductors (ITRS), it is widely believed that a high-k (high permittivity) dielectric is needed to replace SiO2 as the CMOS gate dielectric to reduce significantly the gate leakage current. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance, and thereby drive current and device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-k material allows increased gate capacitance without the leakage effects. The continued shrinking of the CMOS device size for higher speed and lower power consumption drives the conventional SiO2 gate oxide approaching its thickness scaling limit3. Severe direct tunneling and reliability problem at extremely small thickness will set a barrier for given material. Alternative dielectric materials with a higher dielectric constant, k, and thus larger physical thickness than SiO2 will be required to reduce the gate leakage current9 and provide high on-currents. The implementation of high-k dielectrics to the SOI (silicon-on-Insulator) FinFETs improves the scalability and saves chip area. A high-k dielectric material needs to provide good electrical stability, that is, the amount of charge trapped in the high-k dielectric material needs to remain at a low level even after extended operation of a transistor. It should also be scalable, that is, provide an acceptable level of leakage and acceptable levels of electron and hole mobility at a reduced thickness. High-k dielectric materials satisfying these conditions may be advantageously employed for high performance semiconductor devices13. Different materials similarly have different abilities to hold charge. High-k materials, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and titanium dioxide (TiO2) inherently have a dielectric constant or k above 3.9, the k of silicon dioxide. Materials for high-k gate dielectrics include ZrO2, HfO2, other dielectric metal oxides, alloys thereof, and their silicate alloys14.

The dielectric between the plates passes a small amount of leakage current. The conductors and leads introduce an equivalent series resistance and the dielectric has an electric field strength limit, resulting in a breakdown. voltage Thicker gate layer might be used which can reduce the leakage current flowing through the structure as well as improving the gate dielectric reliability.

For both future silicon and emerging non-silicon nanoelectronic transistors15,16 high-k gate dielectric is required for enabling continued equivalent gate oxide thickness scaling, and hence, high performance, and for controlling gate oxide leakage. In addition, high-k gate dielectric is required for successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high Ion /Ioff ratios.

3.1 Threshold Voltage

The threshold voltage VT of a MOSFET is usually defined as the gate voltage where an inversion layer is formed at the interface between the insulating layer (oxide) and the substrate (body) of the transistor16. Threshold voltage is defined as the minimum voltage that is required to make the transistor ON and the drain to source (Ids) current starts conducting18. Threshold voltage in a MOSFET is given by

${V}_{T}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}\frac{\sqrt{2q\epsilon {N}_{A}}}{{C}_{ox}}$

where q = charge of electron (1.6×10-19C), ε = ε0r, ε0 = permittivity of free space (8.854×10-12 F/m), εr, = relative permittivity (3.9 for SiO2), NA = doping concentration, Cox = oxide capacitance.

3.2 Transconductance

In field effect transistors, and MOSFETs, trans-conductance, gm, is the change in the drain current divided by the change in the gate/source voltage with a constant drain/source voltage. Transconductance can be calculated as

${g}_{m}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}\frac{\partial {I}_{D}}{\partial {V}_{GS}}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}\frac{{\epsilon }_{\text{o}}{\epsilon }_{r}}{{T}_{ox}}{\eta }_{n}\text{\hspace{0.17em}}\text{\hspace{0.17em}}W}{L}\left({V}_{GS}-{V}_{T}\right)$

where, μn = mobility of electron, ε0 = permittivity of free space(8.854×10-12 F/m), εr, = relative permittivity(3.9 for SiO2.), Tox =Oxide thickness, W =channel width, L =channel length, VGS=gate-source voltage, VT=threshold voltage.

3.3 Transit Frequency

Transit frequency is the frequency at which the small signal current gain of the device drops to unity while the source and drain terminals are held at ground.

Transit frequency in a MOSFET is given by

${C}_{gs}=\text{\hspace{0.17em}}\frac{2}{3}\text{\hspace{0.17em}}\left(WL{C}_{ox}\right)$

${f}_{t}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}\frac{{\text{ε}}_{\text{o}}{\text{ε}}_{r}{\text{μ}}_{n}W}{2\text{π}{T}_{ox}L{C}_{gs}}{\left({V}_{gs}-{V}_{t}\right)}_{-}$

where, μn = mobility of electron ε0 = permittivity of free space(8.854×10-12 F/m), εr = relative permittivity (3.9 for SiO2), Tox =Oxide thickness, W = channel width, L = channel length, Vgs= gate-source voltage, Vt = threshold voltage, Cox = oxide capacitance.

4.1 Two-dimensional Device Creation

The 2-D device formation and simulations has been done using the Sentaurus Structure Editor of the Technology computer-aided design (TCAD) tool. Figure 2 shows the two-dimensional FinFET device.

The structure consists of two gates, gate 1 and gate 2 and also two fins. The simulations were done for gate voltage values of 0.1, 0.2, 0.5, 0.9, 1.0, 1.5, and 2.0 and also for gate dielectric values of 3.9, 7.8,10, and 23.The drain voltage Vds was kept constant at 2v and the IdVg curve was obtained. The IdVg curve was obtained using Inspect tool.

4.2 Drain Leakage Current

Even though a transistor is logically turned off, there is a non-zero leakage current through the channel at the microscopic level. This current is known as the sub-threshold leakage because it occurs when the gate voltage is below its threshold voltage. Figure 3 shows the variation in drain leakage current with increasing dielectric value and various gate voltages. It is shown that the leakage current is low for high dielectric value, that is, for ε=23(ZrO2), the subthreshold leakage current increases dramatically for low threshold devices. A high threshold voltage in the standby mode gives low leakage current (Ioff).

4.3 Threshold Voltage

Figure 4 shows the variation in threshold voltage (VT) with increasing dielectric value and various gate voltages. It is shown that the threshold voltage is high for high dielectric value that is for ε=23 (ZrO2). The optimum threshold voltage is identified as 0.65 V. A high threshold voltages in the standby mode gives low leakage current (Ioff).

4.4 Transconductance

Transit frequency is the frequency at which the small signal current gain of the device drops to unity while the source and drain terminals are held at ground. Figure 5 shows the variation transconductance (gm) with increasing dielectric value and various gate voltages. It is shown that the transit frequency is high for high dielectric value, that is, for ε=23 (ZrO2), the optimum frequency obtained is 50 MHz.

4.5 Transit Frequency

Transit frequency is the frequency at which the small signal current gain of the device drops to unity while the source and drain terminals are held at ground. Figure 6 shows the variation in transit frequency with increasing dielectric value and various gate voltages. It is shown that the transit frequency is high for high dielectric value that is for ε=23 (ZrO2), the optimum frequency obtained is 50 MHz.

4.6 Gate Capacitance

Plot shows the variation in transit Gate capacitance (Cg) with increasing dielectric value. It is shown that the gate capacitance is high for high dielectric value that is for ε=23 (ZrO2).

4.7 Channel Resistance

Figure 8 shows the variation in channel resistance with increasing dielectric value. It is shown that the channel resistance is low for high dielectric value, that is, for ε=23(ZrO2).

4.8 Gate Delay

Figure 9 shows the variation in gate delay (Td) with increasing gate voltage. The optimum gate delay obtained is 7.0183x10-10 ps.

It is shown that the drain current is also high for high dielectric value, that is, for ε=23(ZrO2).The optimum value of drain current obtained is 0.0035 mA/μm. High-k gate dielectrics enhance CMOS scalability as well as storage capability using NAND gate19 which make it suitable for high speed applications.

Using Technology Computer-Aided Design (TCAD) tools, 2-D device models and simulations can be performed to evaluate the performance of the FinFETs. The optimum value of threshold voltage is identified as VT = 0.653V with 8=23(ZrO2) for the 2-D device structure. For the FinFET device the leakage current has been reduced to 9.47×10-14 A whereas for ε=23 (ZrO2). High-k gate dielectrics enhance CMOS scalability as well as storage capability which make it suitable for high-speed applications. The gate length of the device has to be scaled down to control the parasitic capacitances and the fin thickness is reduced to suppress the short channel effects (SCEs).

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 Mr D. Nirmal received his BE (Electrical and Electronics Engineering) from the Anna University, Chennai in 2005 and ME from Karunya University, in 2007. He is currently pursuing PhD from Anna University, Coimbatore. He is currently focusing on Novel MOS devices for ULSI applications: Transistors with high-k dielectrics. He is now Assistant professor in Electronics and Communication Engineering Department, Karunya University. He is a member of VLSI Society of India (VSI), AMIETE, MSSI(Member of Semiconductor Society of India), life member of Indian Society of Technical Education (ISTE) and active member of several technical associations. He has published many papers in international journals. Dr P. Vijaya Kumar received his BE(Electrical and Electronics Engineering) and his ME (Applied Electronics) from Bharathiar University, in 1992, and 2002, respectively, and PhD from Anna University, Chennai. He is the member of Indian Society of Technical Education (ISTE) and VLSI Society of India (VSI).He has published many papers in international journals. He is now Professor and Head, Electrical and Electronic at the Enginnering Karpagam Engineering College.