| || Fuzzy Logic and VLSI Testing
Author : Kumar, D. Krishna ;Atre, M.V.
Source : Defence Science Journal ; Vol:45(4) ; 1995 ; pp 325-332
Subject : 681.3 Computer Science;621.38 Electronics
Keywords : VLSI testing ;Fuzzy logic
Abstract : A new application of Fuzzy logic (FL), in the context of test vector generation in VLSI testing is presented. Fuzzification of the threshold value simulation (TVS) approach and setting up of mathematical concepts are carried out in terms of a hierarchy of membership functions. The test-vectors are found by optimising a suitable membership function. The Fuzzy model besides giving a different mathematical basis, also helps in defining new and better optimising functions, thus provind its utility. The concepts outlined in this paper, though demonstrated on toy model of a circuit consisting of only AND gates, can easily be extended to circuits with other logic gates.
| || New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Author : Latha, V. ;Atre, M.V.
Source : Defence Science Journal ; Vol:45(3) ; 1995 ; pp 255-265
Subject : 681.3 Computer Science
Keywords : Test vector generation ;Vectors;Combinational circuits
Abstract : A new algorithm for test-vector-generation (TVG) for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.